NEC Electronics plans to introduce 193nm ArF immersion lithography at the 55nm half pitch node (65nm shrink process) as well as hafnium-silicate as a high-k dielectric for both CMOC logic SoC's and embedded DRAM in ultra low power applications.
"With our new process technology, SoC designers will be able to reduce power consumption and costs through device miniaturization compared to conventional 65 nm transistors. The advancements achieved by our UX7LS technology mark another milestone in our continuing effort to pioneer the design and development of revolutionary process technologies to meet ever-changing market demands."

The company expects to have samples shipping by mid-2007 and enter risk/volume production later in the same year.

NEC Electronics claims that its low power process (UX7LS) reduces power consumption in standby mode to approximately one-tenth of conventional 65 nm devices, and also boosts the transistor's on-current by 20 to 30 percent due to the introduction of the hafnium-silicate insulator film.

The company has retained design rules from its 65nm process and with the adoption of immersion lithography the company claims to have reduced the SRAM size to 0.446 square micrometers.

Article comes from FABTECH

http://http://www.fabtech.org/content/view/1587/2/