Last year, we discussed with our readers the challenges that the SSD market would face following the release of new Flash Memory products and the advancements in their technologies; we also touched on the importance of controller IC design, as well as explained the general impact that it would have on the performance of various types of SSDs. For this year, we will be bringing the IC design discussion a step further by focusing on the current state of controller developments and their role in shaping the future of SSD products.

Rise of the PCI-Express Interface

As those who have been following the general developments of the SSD market will be aware, the promotion of SSD products using the PCI-Express interface began as early as 2010. While the early PCI-Express SSDs showed a relatively decent performance when it comes to hardware capability, neither the products' user numbers nor sales momentum had been particularly impressive. One of the main reasons for this, unsurprisingly, has to do with their relatively expensive price, the cause of which can be traced to their hardware and structural designs. Before going over the more specific details concerning PCI-Express SSDs, let us first take a look at the general background of the PCI-e interface and the popular interface that preceded it: the Serial ATA 6.0.

For a long time, what many of the industry's most prominent IC manufacturers and designers believed was that the read and write speeds of SSDs are determined mostly by their interface rather than by the quality of their internal components or IC design. The belief for the most part appears to be a well-founded one: Since 2012, mainstream SSDs known to be based on the Serial ATA 6.0 interface were generally unable to surpass the 550 MB/s limit regardless of the effectiveness of the components used or the speed of the controller ICs. As it became increasingly clear that interface-related limitations are what's restricting a SSD's linear reading and writing speed, the priority of many of the manufacturers had shifted from the traditional SATA interface to alternative solutions that are capable of improving performances as well as transfer speeds. The option that appeared to be the most readily available and flexible for such a purpose was PCI-Express. Unfortunately, as much as it solved speed related issues and boosted hardware performances, there are a few well known problems with the PCI-Express interface that are worth pointing out.

The first major problem, as has been reported in the past, is the extra steps that need to be taken to truly optimize its performance. As the entire line of SSD controllers made before 2013 had been based on the Serial ATA interface, a user who wanted to switch to using PCI-Express would need to apply an extra "bridge chip" on their device in order to convert the Serial ATA and PCI-Express signals. Though the signal conversion between SATA and PCI-e is ultimately faster than that performed between two different SATA interfaces (ie. SATA to SATA), the speed isn’t necessarily fast enough to justify the extra cost incurred from the relatively expensive bridge chips.

Another PCI-e related problem that is worth mentioning concerns hardware specification and compatibility. The SSD's 2.5 inch design, as many will know, is not directly compatible with personal computing devices larger than notebooks. Those who want to use SSDs with their personal desktop computers will either have to spend extra money on installing 2.5-inch-to-3.5-inch adapter brackets or equipping a specially designed expansion chasis. The number of modifications that are required to be implemented before using SSDs in widely used PCs, along with their generally high cost, makes the already limited market for PCI-Express SSDs even smaller, and in turn causes their prices to stay high.

Thankfully, after Intel released the specifications for NVMe in 2008, various manufacturers had begun to develop special drives that potentially lets users boot from their PCI-Express SSDs. This is among the major developments within the IC industry that's boosting the adoption of the PCI-e interface among the masses. Looking at the 2014 data released by the industry's existing IC manufacturers, one would find that virtually all of the controller ICs today have begun to support the PCI-Express interface. Under such support, hardware makers can potentially create thin as well as highly effective devices that are easily compatible with the PCI-e format. Should a consensus eventually be reached among manufacturers to follow a universal set of specs, the PCI-Express interface could eventually become more mainstream within the industry, and be adopted by more and more consumers in the near future.

Key Technologies Used by New LSI SandForce SSDs

LSI SandForce’s recently announced 3000 series is among the company's latest products to support the earlier mentioned PCI-Express interface. Aside from possessing PCI-e compatibility, what’s also noteworthy about the 3000 series’ is its over-provisioning and dynamic over-provisioning features. Before going over the details, let us first take a look at the table below (data obtained from LSI):

First, we need to give credit to LSI for being honest here: a SSD's spare capacity is usually something that's up to the controller manufacturers to determine, and in cases where the limits are not pretty to look at, it's reasonable to be upfront about it, as LSI is with its products. The reason for the limitations is simple: enabling for a lot of spare space in a SSD requires the replacement of more numbers of blocks, so naturally the corresponding capacity that would become available to users would be smaller. This is an unchangeable aspect of Flash memories, and is a rule that has been arduously followed by SandForce since it released its 2200 SSDs.

In the case of the 3000 series, one particularly interesting feature that’s worth talking about is the ability for its Error Code Correction (ECC) function to be adjusted. This feature is made possible through a uniquely implemented technology known "LSI Shield," and is reportedly meant to facilitate the controller manufacturer's entrance into the high-end enterprise SSD market. Through the appropriate adjustments of a SSD's ECC code involving the use of digital signal processing (DSP), both LSI and its manufacturing clients can decide on the intensity of the ECC function for a particular SSD. Stronger intensity generally means better verification codes, higher calculation speeds, and quicker data saving times. These will all end up affecting the overall value of a SSD's available storage capacity.

So, why bother dealing with all the complications? The reason is relatively straightforward-- in the future, many of the flash memories used in SSDs will likely be based on TLC, which is known for their short life spans compared to MLC. In the absence of a strong, reliable protection mechanism, users will unlikely want to place their data inside of any storage systems, let alone pay for them. As for the enterprise level products, even if the longer lived MLC format were ultimately chosen in place of TLC, a user may still end up wanting a few more extra layers of security in their devices. The two internal adjustment features that were mentioned earlier are generally able to improve the reliability of SSDs, but do so at the cost of available capacity and performance. LSI has formally responded to this issue in one of their technical white papers by stating that “there are no perfect storage systems out there.” As having both strong performance and reliability at the same time is technically not possible, manufacturers often have to think hard about striking a proper balance between the two.

One other major LSI features that isn't particularly new but is still worth mentioning is LSI Raise (Redundant Array of Independent Silicon Elements). The main idea behind this feature is that when a SSD "naturally" or "accidentally" fails, it will enter into a "read only” mode which ensures the contents of the storage “can still be properly retrieved." The only thing that can't be reliably performed during this mode, not surprisingly, is the data writing function. Through the proper use of LSI's Raise technology, a user can effectively extend the life of their entire data by cloning it from one SSD device into another.

Below is a comprehensive table listing out all the details for the newest LSI SandForce 3700 series, for anyone who's interested:

Marvell's New Application Technology      

Unlike LSI SandForce, which chooses to convey critical information about its new SSD technologies through white papers, Marvell is known mostly for revealing data about its products in press releases and live exhibitions. Two of the most widely talked about Marvell SSD controllers that are currently gaining a lot of interest are its 88SS9293 and 88SS1083. What's particularly interesting and noteworthy about these two is the relatively low amount of publicity that they’re receiving. The US company's official website has yet to shed any major details on either the 88SS9293 or 88SS1083, for instance, while some of Marvell’s key press releases made only brief mentions about them. The PCI-Express Gen 2 X2 version of the 88SS9293, interestingly, did make a brief appearance at CES 2014 alongside a number of Flash memory components, and was revealed to have a bandwidth of more than 1GB/s.

Where Marvell is currently spending a good majority of its resources these days appears to be in the promotion of the new "SATA Express" interface, which is currently believed to have the potential to exceed the limits of the Serial ATA 6.0Gb/s format. The controller that Marvell is reportedly using to help promote this interface is the 88SS1083 controller, as it is the first to successfully integrate the SATA and PCI-Express signals and is able handle two PCI-Express lanes to achieve ideal transfer speeds.

With Marvell having already elaborated on the details of its ECC technology and data protection before, we will not go into their details here. Readers wanting to get a sense of what can be expected from Marvell's new controller can check out the table below: